1. Field of the Invention
The present invention relates to test circuitry and, in particular, but not exclusively to test circuitry for incorporation in integrated circuits.
2. Discussion of the Related Art
In all but the smallest and simplest of integrated circuits the probability of an error or flaw is such that there is a commercial requirement to perform a test upon the integrated circuit to determine the integrated circuits performance prior to selling the circuit to the end user.
This testing process is automated and features as a step in the production of an integrated circuit. Many different automatic testing protocols have been formulated such as functional tests, scan tests, transition fault tests, and built in self-tests (BIST).
Scan tests and transition fault tests are generally considered to be efficient and are capable of performing extensive testing on the integrated circuit, with scan tests capable of detecting static ‘stuck-at’ faults and the transition fault tests detecting ‘slow-to-rise’ or ‘slow-to-fall’ faults in the circuitry.
‘stuck-at’ faults are faults where a node of the circuit is incorrectly fabricated and retains a constant potential level. ‘slow-to-rise’ and ‘slow-to-fall’ faults are faults where a node is unable to switch between voltage levels within the required time period.
One of the disadvantages of using automatic test equipment and scan testing is that the automatic test equipment clock frequency is limited in speed. These frequency limitations are due to several factors, which include test lead and probe length, the integrated circuit connection pads electrical properties and the test equipment clock switching speeds.
Due to these limitations and the advances in high clock speed integrated circuits it is becoming more common that automatic test equipment clocks are slower than the functional clock rate of the integrated circuit.
This limitation although not affecting the detection of ‘stuck-at’ faults prevents the detection of ‘slow-to-rise’ or ‘slow-to-fall’ faults at the operational frequency of the integrated circuit.
U.S. Pat. No. 6,430,720 describes a ring oscillator on the integrated circuit. This oscillator is used to provide an operational test clock frequency for testing at higher frequencies than provided by the ATE.
“High-Frequency, at-speed Scan Testing”, Lin et al, IEEE Design and Test of Computers, September-October 2003, p 17-25, describes a method for performing an at-speed scan test wherein the circuit at test is supplied by an at-speed on board clock signal created by using PLL circuit controlled by the off-board clock.
The oscillator though has the disadvantage that the ring oscillator is not the functional clock used in operating the circuitry and thus the results produced by the test may not detect all faults exposed during the operation of the circuitry.
Further problems in using the solution from U.S. Pat. No. 64,300,720 occur as the automatic test equipment clock and the test clock are not synchronized. The switching between unsynchronized clock signals can cause glitches in the output clock where cycles are missed or switched in the middle of a clock cycle.
The operating speed of the Automatic Test Equipment is dependent on the standardization of test routines. Test routines are currently modified by hand in order to carry out a wider range of tests. This increases test time which has an impact on the integrated circuit cost. This test routine inflexibility is especially visible in variable capture count testing.